The present invention generally relates to semiconductor devices. More specifically, the present invention relates to data strobe receivers.
There has always been a demand for faster, higher capacity random access memory (RAM) devices. At one time, dynamic random access memory (DRAM) was typically used as the main memory in computer systems. Although the operating speed of the DRAM improved over the years, the speed did not reach that of the processors used to access the DRAM. In a computer system, for example, the slow access and cycle times of the DRAM led to system bottlenecks. These bottlenecks slowed down the throughput of the system despite the very fast operating speed of the system""s processor.
As a result, a new type of memory known as a synchronous dynamic random access memory (SDRAM) was developed to provide faster operation in a synchronous manner. SDRAMs are designed to operate synchronously with the system clock. That is, the input and output data of the SDRAM are synchronized to an active edge of the system clock.
Although SDRAMs have overcome some of the timing disadvantages of other memory devices, such as DRAMs, there is still a need for faster memory devices. Double data rate (DDR) SDRAMs provide twice the operating speed of the conventional SDRAM. These devices allow data transfers on both the rising and falling edges of the system clock and thus provide twice as much data as the conventional SDRAM. DDR SDRAMs are also capable of providing burst data at a high-speed data rate.
Due to the high-speed data transfers, DDR SDRAMs use a bi-directional data strobe (DQS) to register the data being input or output on both edges of the system clock. Industry standards define several states of DQS before, during, and after a burst transfer of data. Before a burst transfer of data, DQS is in a high-impedance state that is known as Hi-Z. When DQS is in Hi-Z, DQS is at a voltage level between logic high and logic low.
One clock cycle before a burst data transfer, DQS transitions from Hi-Z to logic low. This logic low state is known as xe2x80x9cdata strobe preamble.xe2x80x9d After the data strobe preamble, DQS transitions (both low-to-high transitions and high-to-low transitions) are utilized to synchronize the transferred data. One half clock before the data transfer is complete, DQS remains in a logic low state. This state is known as xe2x80x9cpostamble.xe2x80x9d After the completion of the postamble, DQS enters the Hi-Z state.
A need exists for a simple DQS receiver that can accurately determine DQS transitions while utilizing minimal semiconductor die area.
One embodiment of the invention is a data strobe receiver that includes a first comparator. The first comparator has a first input that is coupled to a first reference voltage. The first comparator has a second input that is coupled to a data strobe. The first comparator also has an output. The data strobe receiver also includes a delay element. The delay element has an input that is coupled to the output of the first comparator. The delay element also has an enable input and an output. The data strobe receiver also includes a second comparator. The second comparator has a first input that is coupled to a second voltage reference. The second comparator has a second input that is coupled to the data strobe. The second comparator also has an output. The data strobe receiver also includes a flip-flop. The flip-flop has a preset input that is coupled to the output of the second comparator. The flip-flop has a clock input that is coupled to the output of the delay element. The flip-flop also has an output that is coupled to the enable input of the delay element.
Another embodiment of the invention is another data strobe receiver. This data strobe receiver includes a comparator. The comparator has a first input that is coupled to a data strobe. The comparator has a second input that is coupled to an inverted data strobe. The comparator also has an output. The data strobe receiver also includes a delay element. The delay element has an input that is coupled to the output of the comparator. The delay element also has an enable input and an output. The data strobe receiver also includes a threshold comparator. The threshold comparator has a first input that is coupled to the data strobe. The threshold comparator has a second input that is coupled to the inverted data strobe. The threshold comparator also has an output. The data strobe receiver also includes a flip-flop. The flip-flop has a preset input that is coupled to the output of the threshold comparator. The flip-flop has a clock input that is coupled to the output of the delay element. The flip-flop has an output that is coupled to the enable input of the delay element.